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 Advanced Analog Technology, Inc.
April 2007
AAT1164/AAT1164B/AAT1164C
Product information presented is current as of publication date. Details are subject to change without notice.
TRIPLE-CHANNEL TFT LCD POWER SOLUTION WITH OPERATIONAL AMPLIFIERS
FEATURES
Built in 3A, 0.2 Switching NMOS Positive LDO Driver Up to 28V/5mA Negative LDO Driver Down to -14V/5mA 1 VCOM and 4 VGAMMA Operational Amplifiers 28V High Voltage Switch for VGH Internal Soft-Start Function 1.2MHz Fixed Switching Frequency 3 Channels Fault and Thermal Protection Low Dissipation Current QFN-32 Package Available
GENERAL DESCRIPTION
The AAT1164/AAT1164B/AAT1164C is a triple-channel TFT LCD power solution that provides a step-up PWM controller, two high voltage LDO drivers (one for positive voltage and one for negative voltage), five operational amplifiers, and one high voltage switch up to 28V for TFT LCD display. The PWM controller consists of an on-chip voltage reference, oscillator, error amplifier, current sense circuit, comparator, under-voltage lockout protection and internal soft-start circuit. The thermal and power fault protection prevents internal circuit being damaged by excessive power. The high voltage LDO drivers generate two regulated output voltage (VOUT2 and VOUT3) set by external resistor dividers. VGH voltage does not activate until DLY voltage exceeds 1.25V. The AAT1164/AAT1164B/AAT1164C contains 4+1 operational amplifiers. VO1, VO2, VO4, and VO5 are for gamma corrections and VO3 is for VCOM. In the short circuit condition, operational amplifiers are capable of sourcing 100mA current for VGAMMA, and 200mA current for VCOM. With the minimal external components, the AAT1164/AAT1164B/AAT1164C offers a simple and economical solution for TFT LCD power.
PIN CONFIGURATION
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AAT1164/AAT1164B/AAT1164C
ORDERING INFORMATION
DEVICE TYPE PART NUMBER PACKAGE PACKING TEMP. RANGE MARKING AAT1164 XXXXX XXXX MARKING DESCRIPTION 1. Part Name 2. Lot No. (6~9 Digits) 3. Date Code (4 Digits) 1. Part Name 2. Lot No. (6~9 Digits) 3. Date Code (4 Digits) 1. Part Name 2. Lot No. (6~9 Digits) 3. Date Code (4 Digits)
AAT1164
AAT1164-Q5-T
Q5:VQFN 32-5*5
T: Tape and Reel
-40 C to +85 C
AAT1164B
AAT1164B-Q5-T
Q5:VQFN 32-5*5
T: Tape and Reel
-40 C to +85 C
AAT1164B XXXXX XXXX
AAT1164C
AAT1164C-Q5-T
Q5:VQFN 32-5*5
T: Tape and Reel
-40 C to +85 C
AAT1164C XXXXX XXXX
NOTE: All AAT products are lead free and halogen free.
TYPICAL APPLICATION
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AAT1164/AAT1164B/AAT1164C
ABSOLUTE MAXIMUM RATINGS
PARAMETER VDD to GND VDD1, SW to GND (for AAT1164/AAT1164B) VDD1, SW to GND (for AAT1164C) VOUT3, OUT3, VGH to GND OUT2 to GND Input Voltage 1 (IN1, IN2, IN3, DLY, CTL,) Input Voltage 2 (VI1+, VI1-, VI2+, VI2-, VI3+, VI3-, VI4+, VI4-, VI5+, VI5-) Output Voltage 1 (EO, VREF ) Output Voltage 2 (ADJ, VO1, VO2, VO3, VO4, VO5) Operating Free-Air Temperature Range Storage Temperature Range Power Dissipation SYMBOL VDD VH1 VH1 VH2 VH3 VI1 VI2 VO1 VO2 TC TSTORAGE Pd VALUE 7 13.5 14.5 30 -14 VDD+0.3 VH1+0.3 VDD+0.3 VH1+0.3 -40 C to +85 C -45 C to +125 C 1,600 UNIT V V V V V V V V V
C C mW
Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period of time may affect device reliability.
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AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = -40 C to 85 C , unless otherwise specified. Typical values are tested at 25 C ambient temperature, VDD = 3.3V, VDD1 = 10V.) PARAMETER VDD Input Voltage Range VDD1 Input Voltage Range SYMBOL VDD AAT1164/AAT1164B VDD1 AAT1164C Falling VDD Under Voltage Lockout VUVLO Rising VIN1 = 1.5V, Not Switching VIN1 = 1.0V, Switching VVI1+~VVI5+ = 4V TEST CONDITION MIN 2.6 8 8 2.1 2.3 2.2 2.4 0.56 5.6 7 160 TYP MAX 5.5 13 14 2.3 2.5 0.80 10.0 10 UNIT V V V V V mA mA mA
VDD Operating Current VDD1 Operating Current Thermal Shutdown
IVDD IVDD1 TSHDN
C
Reference Voltage
PARAMETER Reference Voltage Line Regulation Load Regulation SYMBOL VREF TEST CONDITION IVREF = 100A IVREF = 100A, VDD = 2.6V~5.5V IVREF = 0~100A MIN 1.231 TYP 1.250 2 1 MAX 1.269 5 5 UNIT V %/mV %/mA
Oscillator
PARAMETER Oscillation Frequency Maximum Duty Cycle SYMBOL fOSC DMAX TEST CONDITION MIN 1.05 84 TYP 1.20 87 MAX 1.35 90 UNIT MHz %
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AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = -40 C to 85 C , unless otherwise specified. Typical values are tested at 25 C ambient temperature, VDD = 3.3V, VDD1 = 10V.)
Soft Start & Fault Detect
PARAMETER Channel 1 Soft Start Time Channel 2 Soft Start Time Channel 3 Soft Start Time During Fault Protect Trigger Time IN1 Fault Protection Voltage IN2 Fault Protection Voltage IN3 Fault Protection Voltage SYMBOL tSS1 tSS2 tSS3 tFP VF1 VF2 VF3 1.00 0.40 1.00 TEST CONDITION MIN TYP 14 14 14 55 1.05 0.45 1.05 1.10 0.50 1.10 MAX UNIT ms ms ms ms V V V
Error Amplifier (Channel 1)
PARAMETER Feedback Voltage Input Bias Current Feedback-Voltage Line Regulation Transconductance Voltage Gain Gm AV SYMBOL VIN1 IB1 TEST CONDITION MIN 1.221 TYP 1.233 0 0.05 105 1,500 MAX 1.245 40 0.15 UNIT V nA %/mV S V/V
VIN1 = 1V to1.5V
Level to Produce VEO = 1.233V 2.6V < VDD < 5.5V I = 5 A
-40
N-MOS Switch (Channel 1)
PARAMETER Current Limit On-Resistance Leakage Current SYMBOL ILIM RON ISWOFF ISW = 1.0A VSW = 12V TEST CONDITION MIN TYP 3.0 0.2 0.01 20.00 MAX UNIT A
A
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AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = -40 C to 85 C , unless otherwise specified. Typical values are tested at 25 C ambient temperature, VDD = 3.3V, VDD1 = 10V.)
Negative Charge Pump (Channel 2)
PARAMETER IN2 Threshold Voltage IN2 Input Bias Current OUT2 Leakage Current OUT2 Source Current SYMBOL VIN2 IB2 IOFF2 IOUT2 TEST CONDITIONS IOUT2 = -100 A VIN2 = -0.25V to 0.25V VIN2 = 0V, OUT2 = -12V VIN2 = 0.35V, OUT2 = -10V 1 MIN 235 -40 TYP 250 0 -20 4 MAX 265 40 -50 UNIT mV nA
A
mA
Positive Charge Pump (Channel 3)
PARAMETER IN3 Threshold Voltage IN3 Input Bias Current OUT3 Leakage Current OUT3 Sink Current SYMBOL VIN3 IB3 IOFF3 IOUT3 TEST CONDITIONS IOUT3 = 100 A VIN3 = 1V to 1.5V VIN3 = 1.4V, OUT3 = 28V VIN3 = 1.1V, OUT3 = 25V 1 MIN 1.22 -40 TYP 1.25 0 40 4 MAX 1.28 40 80 UNIT V nA
A
mA
High Voltage Switch Controller
PARAMETER DLY Source Current DLY Threshold Voltage DLY Discharge RON CTL Input Low Voltage CTL Input High Voltage CTL Input Bias Current Propagation Delay CTL to VGH VOUT3 to VGH Switch R-on ADJ to VGH Switch R-on VGH to GND1 Switch R-on SYMBOL IDLY VDLY RDLY VIL VIH IB4 tPP RONSC RONDC RONCG VCTL = 0 to VDD OUT3 = 25V VDLY = 1.5V, VCTL = VDD VDLY = 1.5V, VCTL = GND VDLY = 1V 1.5 2 -40 0 100 15 30 2.5 30 60 3.5 k 40 TEST CONDITIONS MIN TYP -5 1.25 8 0.5 V V nA ns MAX -6 1.28 UNIT
-4
1.22
A
V
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AAT1164/AAT1164B/AAT1164C
ELECTRICAL CHARACTERISTICS
(VDD = 2.6V to 5.5V, TC = -40 C to 85 C , unless otherwise specified. Typical values are tested at 25 C ambient temperature, VDD = 3.3V, VDD1 = 10V.)
VCOM and VGAMMA Buffer
PARAMETER Input Offset Voltage Input Bias Current SYMBOL VOS IB5 TEST CONDITIONS VVI1+ ~ VVI5+ = 4V VVI1+ ~ VVI5+ = 4V IVO1, IVO2, IVO4, IVO5 = 5mA, VVI1, VVI2, VVI4, VVI5 = 0V, 4V,10V IVO3 = 50mA, VVI3 = 4V IVO1, IVO2, IVO4, IVO5 = -50mA, VVI1, VVI2, VVI4, VVI5 = 0V, 4V, 10V IVO3 = -50mA, VVI3 = 4V Short Circuit Current ISHORT IVO1, IVO2, IVO4, IVO5 IVO3 VVI1+, VVI3+ = 2V to 8V, VVI3+ ~ VVI5+ = 8V to 2V, 20% to 80% VVI1+ ~ VVI5+ = 3.5V to 4.5V, 90% MIN -40 TYP 2 0 MAX 12 40 UNIT mV nA
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-
VOL
VVI- +0.15
Output Swing
-
4.03
4.06
V
VOH
VVI- -0.15 3.94 -
-
-
3.97
mA mA
100 200
Slew Rate
SR
-
12
-
V/ s
Settling Time
tS
-
5
-
s
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AAT1164/AAT1164B/AAT1164C
TYPICAL OPERATING CHARACTERISTICS
(VIN = 5V, VOUT1 = 12V, VOUT2 = -7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.)
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TYPICAL OPERATING CHARACTERISTICS (CONT.)
(VIN = 5V, VOUT1 = 12V, VOUT2 = -7V, VOUT3 = 27V, TC = +25 C , unless otherwise noted.)
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PIN DESCRIPTION
PIN NO. QFN-32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NAME VOUT3 VERF GND GND1 VO1 VI1- VI1+ VO2 VI2- VI2+ GND2 VI3+ VO3 VDD1 VI4+ VI4- VO4 VI5+ VI5- VO5 SW VDD IN1 EO IN3 I/O O O I I O I I I I I I O I I O I O I DESCRIPTION Channel 3 Output Voltage (gate high voltage input) Internal Reference Voltage Output Ground SW MOS Ground Operational Amplifier 1 Output Operational Amplifier 1 Negative Input Operational Amplifier 1 Positive Input Operational Amplifier 2 Output Operational Amplifier 2 Negative Input Operational Amplifier 2 Positive Input Ground for Operational Amplifiers VCOM Operational Amplifier Positive Input VCOM Operational Amplifier Output High Voltage Power Supply Input Operational Amplifier 4 Positive Input Operational Amplifier 4 Negative Input Operational Amplifier 4 Output Operational Amplifier 5 Positive Input Operational Amplifier 5 Negative Input Operational Amplifier 5 Output Main PWM Switching Pin Power Supply Input Main PWM Feedback Pin Main PWM Error Amplifier Output Positive Charge Pump Feedback Pin
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AAT1164/AAT1164B/AAT1164C
PIN NO. QFN-32 26 27 28 29 30 31 32 NAME OUT3 IN2 OUT2 DLY CTL ADJ VGH I/O O I O I I O O Positive Charge Pump Output Negative Charge Pump Feedback Pin Negative Charge Pump Output High Voltage Switch Delay Control High Voltage Switch Control Pin Gate High Voltage Fall Time Setting Pin Switching Gate High Voltage for TFT DESCRIPTION
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AAT1164/AAT1164B/AAT1164C
FUNCTION BLOCK DIAGRAM
AAT1164/AAT1164B
2 22
VREF 1.233V Reference Voltage 1.25V 0.25V Error Amplifier
VDD Fail Fail / Thermal Control
23 IN1
SW 21 Digital Control Block GND1
4
1. 233V
24
EO
Comparator Current Sense and Limit GND 3 GND2 11 OUT2 28 OUT3 26
Oscillator
27 IN2
0. 25V
25 IN3
1. 25V 6 VI17 VI1+
VO1 5 VO2 8 VO3 VO4
13
9 VI210
VI2+
12 VI3+ 16 VI415 VI4+ 19 VI518
17
VI5+
VO5 20 VDD1 High Voltage Control
14
29 DLY 30
CTL
31
ADJ
32
VOUT3 VGH
1
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AAT1164/AAT1164B/AAT1164C
FUNCTION BLOCK DIAGRAM
AAT1164/AAT1164C
2 22
VREF 1.233V Reference Voltage 1.25V 0.25V Error Amplifier
VDD Fail Fail / Thermal Control
23 IN1
SW 21 Digital Control Block GND1
4
1. 233V
24
EO
Comparator Current Sense and Limit GND 3 GND2 11 OUT2 28 OUT3 26
Oscillator
27 IN2
0. 25V
25 IN3
1. 25V 6 VI17 VI1+
VO1 5 VO2 8 VO3 VO4
13
9 VI210
VI2+
12 VI3+ 16 VI415 VI4+ 19 VI518
17
VI5+
VO5 20 VDD1 High Voltage Control
14
29 DLY 30
CTL
2.5k
31
ADJ
32
VOUT3 VGH
1
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TYPICAL APPLICATION CIRCUIT
Figure 1. Application Circuit
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DESIGN PROCEDURE
Boost Converter Design Setting the Output Voltage and Selecting the Lead Compensation Capacitor
The output voltage of boost converter is set by the resistor divider from the output (VOUT1) to GND with the center tap connected to IN1, where VIN1, the boost converter feedback regulation voltage is 1.233V, Choose R2 (Figure 2) between 5.1k to 51k and calculate R1 to satisfy the following equation.
k=
ILpeak-peak IIN
: Boost converter efficiency
k: The ratio of the inductor peak to peak ripple current to the input DC current VIN: Input voltage VO: Output voltage IO: Output load current fS: Switching frequency D: Duty cycle ILpeak-peak: Inductor peak to peak ripple current IIN: Input DC current The AAT1164 SW current limit ( ILIM ) and inductor's
V R1 = R2 OUT1 - 1 VIN1
VOUT1
saturation current rating ( ILSAT ) should exceed IL(peak), and the inductor's DC current rating should exceed IIN. For the best efficiency, choose an inductor with less DC series resistance ( rL ).
EO 24 RC CP CC GND gm
VREF IN1 23
R1 VIN1 R2
ILIM and ILSAT > IL(peak )
ILDC > IIN
GND
IL(peak) = IIN +
VIND , 2LfS
Figure 2. Feedback Circuit
IIN =
IO , (1 - D)
2
Inductor Selection
The minimum inductance value is selected to make sure that the system operates in continuous conduction mode (CCM) for high efficiency and to prevent EMI. The equation of inductor uses a parameter k, which is the ratio of the inductor peak to peak ripple current to the input DC current. The best trade-off between voltage ripple of transient output current and permanent output current has a k between 0.4 and 0.5.
VO L D(1 - D)2 , kIO fS
V D = 1 - IN VO ,
IO PDCR rL (1 - D)
ILDC: DC current rating of inductor PDCR: Power loss of inductor series resistance Table 1. Inductor Data List rL DC CURRENT RATING
C6-K1.8L
3.9H 6.8H 10H
41m 68m 81m
2.5A 2.2A 1.8A
MITSUMI Product-Max Height:1.9mm
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AAT1164/AAT1164B/AAT1164C
Example 1: In the typical application circuit (Figure 1) the output load current is 300mA with 13.3V output voltage and input voltage of 5V. Choose a k of 0.431 and efficiency of 90%.
0.9 * 13.3 0.624(0.376)2 6.8 H
For example, PDIODE = PDSW + PDCOM = 0.0273W or 0.68% power loss.
Input Capacitor Selection
The input capacitors have two important functions in PWM controller. First, an input capacitor provides the power for soft start procedure and supply the current for the gate-driving circuit. A 10 F ceramic capacitor is used in typical circuit. Second, an input bypass capacitor reduces the current peaks, the input voltage drop, and noise injection into the IC. A low ESR ceramics capacitor 0.1 F is used in typical circuit. To ensure the low noise supply at VDD, VDD is decoupled from input capacitor using an RC low pass filter.
0.431* 0.3 * 1.26 IO IIN = = 0.886A (1 - D)
L
VD IL(peak ) = IIN + IN = 1.0778A 2LfS PDCR = 0.0534W or 1.34% power loss
Schottky Diode Selection
Schottky has to be able to dissipate power. The dissipated power is the forward voltage and input DC current. To achieve the best efficiency, choose a Schottky diode with less recovery capacitor (CT) for fast recovery time and low forward voltage (VF). For boost converter, the reverse voltage rating (VR) should be higher than the maximum output voltage, and current rating should exceed the input DC current. PDIODE = PDSW + PDCOM PDSW = (1-D) VFQRfS QR = VRCTQR PDCOM = VFIO (1-D) PDIODE: Total power loss of diode for boost converter PDSW : Switching loss of diode for boost converter PDCOM: Conduction loss of diode for boost converter
VDD VDD
Figure 3. Input Bypass Capacitor Affects the VDD Drop.
Output Capacitor
The output capacitor maintains the DC output voltage. A Low ESR ( rC ) ceramic capacitor can reduce the output ripple and power loss. There are two parameters which can affect the output voltage ripple: 1. the voltage drops when the inductor current flows through the ESR of output capacitor; 2. charging and discharging of the output capacitor also affect the output voltage ripple. VRIPPLE = VRIPPLE (COUT ) + VRIPPLE (ESR)
Table 2. Schottky Data List
SMA B220A B240A VF 0.24V 0.24V VR 14V 28V CT 150pF 150pF
DIODES Product-Max Height: 2.3mm
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AAT1164/AAT1164B/AAT1164C
VRIPPLE (COUT ) IO D fS COUT
VRIPPLE (ESR) I L(peak) rC
V IC(rms) = O RL D D (1 - D)RL 2 + [ ] 1 - D 12 LfS
PESR = IC(rms)
(
)
2
rC
Figure 4. Closed-Current Loop for Boost with PCM
ESR: Equivalent Series Resistance Example 2: COUT = 38F, rC = 20 m
VRIPPLE (COUT ) = 4.1mV VRIPPLE (ESR) = 21.5mV VRIPPLE = 25.6mV IC(rms) = 0.411A PESR = 0.00338W or 0.08% power loss
+ +
-
-
Boost Converter Power loss
The largest portions of power loss in the boost converter are the internal power MOSFET, the inductor, the Schottky diode, and the output capacitor. If the boost converter has 90% efficiency, there is approximately 7.89% power loss in the internal
-
+
MOSFET, 1.34% power loss in the inductor, 0.68% power loss in the Schottky diode, and 0.08% power loss in the output capacitor.
Figure 5. Block Diagram of Boost Converter with Peak Current Mode (PCM)
Power Stage Transfer Functions
The duty to output voltage transfer function Tp is:
Loop Compensation Design
The voltage-loop gain with current loop closed sets the stability of steady of state response and dynamic loop performance transient response. The
Tp (s) =
VO (s + esr )(s - z2 ) = Tp0 d s2 + 2n s + n2
-rC 1 , esr = COUTrC 1 - D )( RL + rC ) (
Where Tp0 = VO And
compensation design is as follows:
z2 =
RL (1 - D ) - r L
-
2
, n =
(1 - D )2 RL + r LCOUT (RL + rC )
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AAT1164/AAT1164B/AAT1164C
= COUT [r (RL + rC ) + RL rC (1 - D ) ] + L 2 LCOUT (RL + rC ) [r + (1 - D ) RL ] r = rL + DrDS + (1 - D)RF
rL is the inductor equivalent series resistance, rC is capacitor ESR, RL is the converter load resistance, COUT is the output filter capacitor, rDS is the transistor turn on resistance, and RF is the diode forward resistance. The duty to inductor current transfer functionTpi is: i s + zi Tpi (s) = l = Tpi0 2 d s + 2n s + n2
2
,
Ticl (s) =
s2 + 2n s + n2 12fS2 x RCS Tpi0 ( s + ) s2 + s +12f 2 zi sh S
(
)
(
)
The Voltage-Loop Gain with Current Loop Closed
The control to output voltage transfer function Td is:
Td (s) =
VO (s) = Ticl (s)Tp (s) VC (s)
The voltage-loop gain with current loop closed is:
L VI (s) = TC (s)Td (s)
2 s + c 12fS Tp0 x s R CS Tpi0
Where Tpi0 =
VO (RL + 2rC ) 1 , zi = COUT (RL / 2 + rC ) L (RL + rC )
= gm R C
Current Sampling Transfer Function
Error voltage to duty transfer function Fm (s) is:
( s + z1 )( s - z2 ) ( s + zi ) (s2 + ssh + 12fS2 )
V Where = FB VO
2fS2 s2 + 2n s + n2 d Fm (s) = = Vei Tpi0RCS s ( s + zi )( s + sh )
Where sh
(
)
The compensator transfer function
3s 1 - M2 - Ma = 1+ , = M + M , 1 a
TC (s) =
s = 2fS
Therefore, Fm(s) depends on duty to inductor current transfer function Tpi(s), and fS is the clock switching frequency; RCS is the current-sense amplifier transresistance. For the boost converter M1 = VIN / L and M2 = (VO-VIN) / L. For AAT1164, RCS = 0.24 V/A, Ma is slope compensation, Ma = 0.8x10
6.
VC s + c = gmRC , Vfb s
Where
c = 1 RCCC
The closed-current loop transfer function Tpi(s) is:
Figure 6. Voltage Loop Compensator
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AAT1164/AAT1164B/AAT1164C
Compensator design guide:
Bode Diagram 60
Magnitude (dB) Phase (deg)
1 1. Crossover frequency fci < fS 2
2. Gain margin>10dB 3. Phase margin>45 4. The L VI (s) = 1 at crossover frequency, Therefore, the compensator resistance, RC is determined by:
40
20
0
-20
-40 -90
-135
-180
-225
-270
(RL + 2rC ) V 2fciCOUTRCS RC = O VFB gmk r (1 - D ) RL - (1 - D )
Table 3. k Factor Table Best Corner
Frequency 23.740kHz 21.842kHz 20.095kHz 15.649kHz 13.247kHz
10
2
10
3
10 Frequency (Hz)
4
10
5
10
6
Figure 7. Bode Plot of Loop Gain Using Matlab Simulation
(R)
COUT
k Factor 4.692 5.083 6.042 5.230 4.703
Positive and Negative LDO Driver Output Voltage Selection
The output voltage of positive LDO driver is set by a resistive divider from the output (VOUT3) to GND with the center tap connected to the IN3, where VIN3, the positive LDO driver feedback regulation voltage, is 1.25V. Choose R6 (Figure 8) between 10k calculate R5 with the following equation. and 51k . And
21.533F 25.079F 32.587F 36.312F 38.469F
5. The output filter capacitor is chosen so COUTRL pole cancels RCCC zero
V R5 = R6 OUT3 - 1 VIN3
The output voltage of negative LDO driver is set by a resistive divider from the output (VOUT2) to VREF with the center tap connected to IN2, where VIN2, the negative LDO driver feedback regulation voltage, is 0.25V. Choose R9 (Figure 9) between10k and
R RCCC = COUT L + rC , and 2 C R CC = OUT L + rC RC 2
= (1 ~ 3) Example 3:
51k VIN = 5V, VO = 13.3V, IO = 300mA, fS = 1,190kHz, VFB = 1.233V, L = 6.65H, gm = 85S, rL = 76.689 m rC = 9.13 m RF = 0.7667
RC = 7.6 k
,
and calculate R8 with the following equation.
V - VOUT2 R8 = R9 IN2 VREF - VIN2
, CC = 1.95nF,
, COUT = 38.5 F , = 3, RCS = 0.23V/A.
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C5 1F C6 1F R4 6.8k OUT3 26 C7 1F
April 2007
AAT1164/AAT1164B/AAT1164C
used. BAT54S (Figure 8 and 9) has fast recovery time
VOUT1 13.3V/300mA
and low forward voltage for best efficiency.
U1 BAT54S
LDO Driver Base-Emitter Resistors
For AAT1164, the minimum drive current for positive and negative LDO drivers are 1mA, thus the minimum base-emitter resistance can be calculated by the
VOUT3 25V/30mA
Q1 MMBT4403
SW
IN3 25
R5 200 k C8 1F
U2 BAT54S
following equation:
R6 10k
VOUT3 1
R 4 (min) VBE(max) / ((IOUT3(min) - IC ) / hfe(min) ) R 7(min) VBE(max) / ((IOUT2(min) - IC ) / hfe(min) )
Figure 8. The Positive LDO Driver Table 4. Pass Transistor Specifications MMBT4401 MMBT4403
VBE(max)
hfe(min)
0.65V 130
0.5V 90
DIODES Product, Package: SOT23
Example 5: Output current of VOUT3 and VOUT2 are 30mA, the minimum base-emitter resistor can be calculated as
Figure 9. The Negative LDO Driver
Example 4: For system design VOUT3 = 25V, R5 = 200k , R6 = 10k , VOUT2 = -6V, R8 = 62k , R9 = 10k
R 4 (min) 0.5 / (( 1mA - 30mA ) / 90) 750 R 7(min) 0.65 / (( 1mA - 30mA ) / 130) 845
The minimum value can be used, however, the larger value has the advantage of reducing quiescent current. So we choose 6.8k to be R4.
Flying Capacitors
Increasing the flying capacitor (C5, C7, C9) values can lower output voltage ripples. The 1F ceramic capacitors works well in positive LDO driver. A 0.1F ceramic capacitor works well in negative LDO driver.
Charge Pump Output Capacitor
Using low ESR ceramic capacitor to reduce the output voltage ripple is recommended and output voltage ripple is dominated by the capacitance value. The minimum capacitance value can be calculated by the following equation:
LDO Driver Diode
To achieve high efficiency, a Schottky diode should be
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ILOAD 2Vripple fS
April 2007
AAT1164/AAT1164B/AAT1164C
COUT
Example 6: The output voltage ripple of VOUT3 and VOUT2 is under 1%, the minimum capacitance value can be calculated as
COUT (VOUT3 ) COUT (VOUT2 )
30mA 0.1F 2 x 250mV x 1.19MHz 30mA 0.33F 2 x 60mV x 1.19MHz
: Efficiency, about 60% at charge pump circuit
Table 5. Recommended Components DESIGNATION DESCRIPTION 6.8 H, 1.8A, L MITSUMI C6-K1.8L 6R8 200mA 30V Schottky barrier diode (SOT-23), U1, U2, U3 DIODES BAT54S 2A 20V rectifier diode D DIODES DFLS220L
C3 C5, C6, C7 C2, C4, C9, C10, C12 10 F, 25V X5R ceramic capacitor 1 F, 25V X5R ceramic capacitor 0.1 F, 50V X5R ceramic capacitor
Operational Amplifier
The AAT1164 has five independent amplifiers. The operational amplifiers are usually used to drive VCOM and the gamma correction divider string for TFT-LCD. The output resistors and capacitors of amplifiers are used as low pass filters and compensators for unity gain stable.
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AAT1164/AAT1164B/AAT1164C
Soft Start Waveform
LAYOUT CONSIDERATION
The system's performances including switching noise, transient response, and PWM feedback loop stability are greatly affected by the PC board layout and grounding. There are some general guidelines for layout:
supply. The ground connection of the VDD and VREF bypass capacitor should be connected to the analog ground pin (GND) with a wide trace.
Output Capacitors
Place output capacitors as close as possible to the IC. Minimize the length and maximize the width of traces to get the best transient response and reduce the ripple noise. We choose 10F ceramics capacitor to reduce the ripple voltage, and use 0.1F ceramics capacitor to reduce the ripple noise.
Inductor
Always try to use a low EMI inductor with a ferrite core.
Filter Capacitors
Place low ESR ceramics filter capacitors (between 0.1F and 0.22F) close to VDD and VREF pins. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner voltage
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Feedback
If external compensation components are needed for stability, they should also be placed close to the IC. Take care to avoid the feedback voltage-divider resistors' trace near the SW. Minimize feedback track lengths to avoid the digital signal noise of TFT control board.
April 2007
AAT1164/AAT1164B/AAT1164C
Ground Plane
The grounds of the IC, input capacitors, and output capacitors should be connected close to a ground plane. It would be a good design rule to have a ground plane on the PCB. This will reduce noise and ground loop errors as well as absorb more of the EMI radiated by the inductor. For boards with more than two layers, a ground plane can be used to separate the power plane and the signal plane for improved performance.
PC Board Layout
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AAT1164/AAT1164B/AAT1164C
PACKAGE DIMENSION
VQFN32
PIN 1 INDENT C
b
E
E2 e
A1 D A D2 L
Symbol
A A1 b C D D2 E E2 e L y
Dimensions In Millimeters MIN TYP MAX 0.8 0.9 1.0 0.00 0.02 0.05 0.18 0.25 0.30 -----0.2 -----4.9 5.0 5.1 3.05 3.10 3.15 4.9 5.0 5.1 3.05 3.10 3.15 -----0.5 -----0.35 0.40 0.45 0.000 -----0.075
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